1. Field of the Invention
The present invention relates to a signal processing circuit for multiplication and, more specifically, to a structure of a digital filter suitable for higher degree of integration.
2. Description of the Background Art
Recently, signal processing which has been carried out in an analog manner has come to be carried out digitally in various fields. A circuit structure called a digital filter is one device that performs digital signal processing. FIG. 1 schematically shows a structure of a signal processing apparatus employing a conventional digital filter.
Referring to FIG. 1, the signal processing circuit comprises a digital filter 11 and a D/A converter 12 for converting digital signals into analog signals. The digital filter 11 receives a digital signal X sampled at a prescribed period through an input terminal 1 and a digital signal C determining characteristics of the filter through an input terminal 2. The digital filter 11 processes the digital signal X in accordance with the filter characteristics determined by the digital signal C, and outputs the result of processing to the D/A converter 12.
The D/A converter 12 converts the digital signal from the digital filter 11 into an analog signal which is outputted as an output signal I at an output terminal 3.
FIG. 2 shows one example of a specific structure of the digital filter 11 shown in FIG. 1. The filter structure shown in FIG. 2 is generally known as a FIR (Finite Impulse Response) type digital filter. Referring to FIG. 2, the digital filter 11 comprises three stages of cascade connected delay circuits 4a, 4b and 4c, multipliers 13a, 13b, 13c and 13d multiplying the input signal X and the outputs from the respective delay circuits 4a to 4c by corresponding coefficients Ca to Cd, respectively, to output the results, and an adder 14 for adding the outputs from the multipliers 13a to 13d. Each of the delay circuits 4a to 4c delays an applied signal for a prescribed time period, and outputs the same in response to a clock signal from a clock generator, not shown.
The multiplier 13a multiplies the digital signal X from the input terminal 1a by the multiplication coefficient Ca to output the result. The multiplier 13b multiplies the output from the delay circuit 4a by the multiplication coefficient Cb to output the result. The multiplier 13c multiplies the output from the delay circuit 4b by the multiplication coefficient Cc to output the result. The multiplier 13d multiplies the output from the delay circuit 4c by the multiplication coefficient Cd to output the result. A digital output signal Y is outputted from the adder 14.
The multiplication coefficients Ca, Cb, Cc and Cd are applied to the multipliers 13a to 13d through terminals 2a, 2b, 2c and 2d. By changing the values of the multiplication coefficients (digital signals) Ca, Cb, Cc, and Cd, the multiplication values in the multipliers 13a to 13d are changed, so that the characteristics of the digital filter 11 can be changed.
When a signal processing which has been carried out by an analog filter is to be done by a digital filter, the output of the digital filter must be converted to an analog signal through the D/A converter 12, as shown in FIG. 1. Generally, the D/A converter 12 is formed on a chip separate from the digital filter, thereby increasing the size of the signal processing apparatus.
A conventional digital filter, one example of which is shown in FIG. 2, comprises delay circuits, multipliers and an adder. The speed of operation of the multipliers must be increased to realize a high speed digital filter. However, since these multipliers generally consist of full adders, ripple carries and the like must be generated for transmitting carries to the next stages, so that delays are generated due to the carries. In addition, the maximum propagation path of the signal is elongated for generating such carry, which decreases the speed of operation in the multipliers. These problems become more conspicuous as the bit length of the digital signals to be processed becomes longer.
Even when the multiplication coefficients of the digital filter are set in advance and fixed during the operation of the filter, the maximum propagation path of the signal in the multipliers is kept as it is. Therefore, the fact that the maximum propagation path of the signal becomes longer leads to signal propagation delay in the multipliers, which prevents high speed multiplication.
In order to increase the speed of operation of the multipliers, the structure of the multiplier may be implemented in pipelines. In that case, however, the structure of the apparatus becomes complicated and the area of the circuitry is increased.
The general structure of the FIR digital filter, examples and methods of implementing filter elements such as adders and multipliers included in the digital filter are disclosed in "Special-Purpose Hardware for Digital Filtering", S. L. FREENY, Proceedings of the IEEE, Vol. 63, No. 4, April 1975, pp. 633-648.